1. Field of the Invention
The present invention relates to a semiconductor memory device having a planar cell structure.
2. Description of the Related Art
In general, an MOS type semiconductor integrated circuit device is formed in such a way that a field oxide film is used for device isolation and that a source region and a drain region are formed by diffusing impurities in a substrate by a self-alignment method with the use of a gate electrode as a mask. One or two contacts are required for connecting the source region and the drain region per one transistor. Therefore, space is needed for margine for the contacts and wiring, which impedes the realization of a minute and compact device.
In order to improve this point, a semiconductor integrated circuit device having a planar cell structure has been proposed in Japanese Patent Application Laying Open (KOKAI) Nos. 61-288454 and 63-96953, for example.
In the planar cell structure, a first continuous diffusion area for a plurality of MOS transistor source regions and a second continuous diffusion area for a plurality of MOS transistor drain regions are formed in parallel to each other on a substrate. A word line is formed on the substrate crossing over the first and second diffusion areas through an electrically insulating film.
In accordance with the planar cell structure, it becomes unnecessary to form a field oxide film for device isolation. Also, the source region and the drain region are formed in common to a plurality of MOS transistors. Therefore, only one contact is needed for several or more transistors, which makes it possible to realize a compact IC device of high density.
In the planar cell structure, it is desirable that a relatively thick insulating film be formed on the diffusion areas since the word line is formed crossing over the diffusion areas for the source and drain regions. This is because if the insulating film is thin, the capacity between the diffusion area and the word line, resulting that the functional speed is lowered.
To the contrary, however, with respect to the channel region, the gate oxide film have to be thin to make the structure minute and compact and obtain a high speed function thereof.
In accordance with the planar cell structure, the resistance of the bit line becomes high, since the bit line is constituted from the continuous diffusion layer in common to a plurality of memory transistors. The transmission speed of a memory signal of a memory device is determined from the product of the bit line resistance and the capacity. Therefore, it is one way to lower the resistance of the bit line in order to raise the transmission speed of the memory signal.